Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHmmm.... The standard Altera UART seems to only have a 1x clock input. Even if it uses both edges that isn't enough to (easily) decode async.
The fifo uart only seems to have pre-defined baud/divisors, so it is difficult to verify from the docs. If the data isn't oversampled then it will go wrong.