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Altera_Forum
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14 years ago

Error: Connected system ID hash not found on target at expected base address

Hello,

Usual sentence first: I'm fairly new to FPGA programming, so bear with me.

I tried to follow the Nios II Hardware Development Tutorial (version 3.0, Dec. 2009) using the latest (v 11.0) tools (Quartus II, Nios II Tools etc.) on Windows 7.

Everything works relatively smoothly (only problem is a timing issue with the JTAG, which I can't solve but can be ignored if I understand correctly). The .sof is written onto the FPGA. It consists of a cpu, onchip_mem, sysid, led_pio (it's a Cyclone III eval board), sys_clk_timer and a jtag uart.

The tutorial uses the count_binary sample and everything compiles without error. However, if I try to do Run As -> Nios II Hardware a windows pops open telling me "connected system id hash not found on target at expected base address."

If I click System ID Properties I get:

Expected system ID base address: 0x11030 (which is the one in the SOPC builder)

Expected system ID: 0x0 (which is the one in the SOPC builder)

connected system id: not found

Expected system timestamp: 1306314921

connected system timestamp: not found

I can see the connected USB-Blaster in the Processors and Byte Stream Devices panel.

Any suggestions would be much appreciated

U.

27 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yeah, it connects to 8 LEDs where I have only 4. I just want to run something simple to see if there is any connection between the Nios II Eclipse tool and the FPGA.

    The error messages Altera provides are absolutely rubbish. They don't tell what is going wrong and they are nowhere referenced so that you look up where it comes from. I'm quite frustrated with this company already
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    In the Target connection check the boxes ignore mismatch id and mismatch time stamp.

    Probably the sysid of ur sopc is not matching with the id in the nios2.It is a common issue.

    Now I am working like that.It does not effect the design.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    If I tick the boxes in the Run As Configuration that makes Nios to ignore the ID and timestamp values from the sysid, I get an error saying "Downloading ELF process failed". I think there must be something wrong with the communication to the board, but can't figure out what it is.

    Cheers,

    U.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Have you actually got the JTAG connection to the card working at all?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Sorry for being thick, but I don't know. I just follow the tutorial. I have no idea how to test if it's working or not. Unfortunately the tutorials don't tell you what you are actually doing, which I find very unsatisfactory. I just added the components and hoped it works to find out later what I actually did.

    U.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Have you told the software what type of JTAG host interface you are using?

    (IIRC the options are USB, network etc)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Which software? SOPC Builder, Nios Tool, Quartus? All very confusing. How do I test the if the JTAG is working?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It s ok don't worry if you have followed any tutorial..the design are all correct. I have used them.. I know there is a problem of the error you are getting.I had the same problem but there is a work around to it.

    First check

    Do you have a jtag component in ur sopc..if not add it..did you donwload the hardware design in the fpga??

    Donot terminate the programmer open sopc ,the time limited which is running.

    Go to eclipse select perspective..goto debug configurations..check if u can see the cable which u are using to download..now debug it..donot run it..

    I don't know the cause of the error but it woorks fine,there will be a warning of terminated but don't worry you can run it..use debug
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    OK, thanks for that. I get a new error message now, which says

    "The system console model is invalid. Cannot launch."

    But that could be because the programme count_binary seems to be written for different hardware test board. I have the Cyclone III starter kit and the programme addresses LCD etc, which don't exist on that one but the Cyclone III Development kit.

    I'm still not sure if it's talking to the FPGA
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Count_Binary connects to lcd and an led.If you have led it should work.Check the design for proper connections.