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Altera_Forum
Honored Contributor
12 years agoI got the same problem when using Quartus II 12.0 with Altera UniPHY IP.
For my case, the error is introduced by the input clock for sysid module that connects to UniPHY afi_half_clk. As reported in following thread, afi_half_clk from UniPHY is stuck to 0. DDR2 SDRAM with UniPHY not generating half_rate_clock: http://www.alteraforum.com/forum/showthread.php?t=39884