Error (10170): Verilog HDL syntax error at sha256_pipe.v

Hello all,

I got the following error while trying the Verilog HDL. I'm using Quartus II 13.0.

Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "}"

Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "<=", or "="

Here is the code:

data15_p1 <= `S1( SS[i-1].data[`IDX(15)] );

Can anyone assist please, because I am stumped.

Thanks in advance,