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Altera_Forum
Honored Contributor
14 years agoI Found it!
The EPCS's 0x800 byte address space consists of a 0x400 byte ROM in the lower half and an SPI controller in the upper half. For some reason, the BSP generates the line: EPCS_FLASH_CONTROLLER_0_REGISTER_OFFSET 512 in system.h. The correct value should be 1024 since the SPI registers begin after the end of the 0x400 byte ROM. This error ultimately causes an incorrect base address to be passed into alt_avalon_spi_command(base). Once I changed the line to: EPCS_FLASH_CONTROLLER_0_REGISTER_OFFSET 1024 everything works fine.