EPCS fpga+nios field update

Thanks Kevin, but but I'm still not able to run the second software image in my EPCS.

I change the sources in the boot_loader_files directory and run a make from the EDS command line tool.

I can see that there is a epcs_controller_boot_rom_synth.hex file in my SOPC directory. But I do not understand where this file is coming from. Is this . Is this an ELF converted to HEX when the SOPC generates the NiosII and is coming from the boot_loader_sources/obj directory?

1) I changed the boot_loader_epcs_bits_sii_siii_ciii.S everywhere where I find sub_epcs_open_address:

//First of all I define the base address off the second image (first SOF, ELF is after SOF)

movi r_reconfig_image_base, SECOND_IMAGE_ADDRESS

// Close & re-open EPCS where we will start extracting the length

addi r_flash_ptr, r_reconfig_image_base, 48

// Close & re-open EPCS at byte 33

addi r_flash_ptr, r_reconfig_image_base, 33

2) Then I recompile with the make command in this directory

3) I open the FPGA project of the Second Application and replace the EPCS bootloader in SOPC builder and build again.

4) In Quartus Update Memory Initialisation file and recompile the Quartus project.

5) Then I convert my ELF and SOF files to hex files and create a JIC file and project this

But still my first software image is loaded by the bootloader.

I would expect that my second NiosII does not run at all but I do not expect that it would run the first software image in my EPCS device.

Does any one has a simple bootloader example of Cyclone III with a fixed second software image?