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Altera_Forum
Honored Contributor
15 years agoentering superloop niche while using uCOS ?
Dear all, Currently I'm developing a gigabit ethernet interface project on Stratix IV. The FPGA has to receive data continuously from a DSP board and transmit them to PC. The connection between...
Altera_Forum
Honored Contributor
15 years agolike the name says, to find out what is happening you need to run your application with a debugger and put a breakpoint on dtrap(). Then when the debugger stops, go up in the function call list and find out where dtrap() was called. If you are lucky you'll find a comment next to the call saying what the problem is. The Interniche stack developers were too lazy to write real error messages.