Honored Contributor
Honored ContributorI now have the FLASH Tri-State generic controller and Tri-State pin sharing working and can read the various regions of the FLASH via NIOS II .
I am able to run the elf2flash command with the --boot parameter. The command I have is below. elf2flash --base=0x01000000 --end=0x01ffffff --reset=0x01800000 --input=cyclone_sw_flash.elf --output=nios_flash_sw.flash --boot=boot_loader_cfi.srec And I get a warning that the start address in the .elf is not the same as the reset address, but the output file is generated and reviewing it indicates the boot_loader_cfi.srec file is at the start of the file. Is the warning expected or do I need to dig into the .elf file to figure out how to avoid the warning. I can commit the output file to FLASH using the undate portal and dump the user space of the FLASH , indicating the nios_flas_sw.flash file was programmed at offset 0x00800000 in the FLASH. The problem is that I then think I need to go back to the FPGA design and alter the NIOS II reset vector to point to 0x01800000, the start of the user software space where the start of the boot loader resides. When I do that and then run sof2flash command on the .sof to generate a *_hw.flash file and commit it to FLASH using the update portal the FPGA loads from FLASH but the NIOS II code doesn't appear to run. Am I missing some step ? The alternative to moving the reset vector from SSRAM to FLASH would be to swap the mapping of the FLASH and the SSRAM. I have not tried that .
