Dude, where are my JTAG pins

Thanks Jake

Unfortunately I have thoroughly looked at these documents and I do not feel that they are pointing me in the right direction.

From what I can see the only usefull simulation advice in these documents refers to either at an sopc level (the sopc functionality on its own not as part of a bigger design) or physically exercising the design in the actual hardware.

What I am after is some way to drive the (invisible) Jtag pins from the device top-level (with the sopc block buried within the device) for the purpose of simple software independant sopc register writes / reads during an RTL simulation.

This is required as part of our system testing (and follows a standard design flow).

I assume there is some method of doing this by using the RTL testbench, a tcl script, or a combination of the two. The trouble is I cannot find any information on this.

Using command windows like system console is fine for testing the physical hardware implementation. However I cannot find a way to do this under RTL simulation conditions (I have looked at the PLI, but it is not supported for the sopc Jtag UART).

I am sure the information I need exists somewhere but I cannot find this in any of the multiple searches that I have done.

Please advise.

Thanks,

Winston. :)