Dual port memory corruption

We do need TCM with OLD_DATA - doesn't matter if it is the s1 or s2 side (assuming that warning only applies to s2).

We can do some experiments with qsys - but not on the real project.

(The PCIe to avalon bus component isn't supported (or is different) - so that has to be changed.)

Or does OLD_DATA enforce a read-latency of 2?

Neither nios cpu has a data cache - the frequently accessed memory is tightly coupled.

Changing the shared memory to use the Avalon interface (ie not dual ported to TCM) wuold also slow down the cycles too much.

Adding mutex isn't possible, the one cpu doesn't have enough free clock cycles to acquire them.

The one 'mutex' I have that cpu does a 'trylock()' action and takes a dufferent path if the mutex can't be obtained.

I did a quick audit of the locations that might have issues earlier in the year, I remember that at least some of them were very problematic.