Dual port memory corruption

That might explain why the Qsys on-chip memory component issues the following warning when in dual port, single clock mode:

Info: onchip_memory2_0: Tightly Coupled Memory operation is not supported with s2 Avalon interface during single clock operation.

If you have an easily reproducible case perhaps manually editing the HDL to force it back into single clock mode would determine if it's worth exploring a solution to that problem. If that solves it then it might be possible to create a custom tightly coupled memory, I can't remember which tool prevents this but I seem to recall someone managed to get that working once.... I'm just not sure if it was in SOPC Builder or Qsys. How many memory locks do you need? Perhaps you can add a mutex component and use it as the locking mechanism instead to avoid the simultaneous read-write to the same address

If you have a lot of memory locks perhaps a secondary small single port memory could be used for your locking mechanism, but that would require a regular data master connections and cache bypassing. Last but not least another technique I like using for message passing (especially if it's frequent) are FIFOs, but that requires a pair if you want to move messages in both directions.