Dual port memory corruption

Both ports to the memory should be on the same clock. The same same 100MHz clock is fed to the nios (using it as a tightly coupled data memory), the other nios (accessing via the avalon bus) and the memory interface itself.

I've just had a thought, the only other avalon master (to this particular memory block) is the PCIe slave. That will require a clock crossing bridge and a bus-width adapter. Will those be generated separately for each slave? Or will the interface be converted once?

Is there an easy way to tell??

If the former, maybe we should add the explicit bridges?

Plausibly having two separate sets of bridges might actually work best.

One to map the top 16MB of the BAR to the SDRAM (optimised for burst transfers).

The other to map the low 16MB to various on-chip resources (optimised for single word transfers, this could alias addresses at 256kB ).

I'm not sure we've really looked at any of the avalon bridges.

If relevant we are 'still' using Q9.1sp2, moving forwards is causing grief.