Dual port memory corruption

Everything is running off the same 100MHz clock.

I don't remember there being options in the sopc builder for read latency - but it is a while since I've used it - any values are likely to be the defaults.

This part of the fpga (it is a large Arria part) is a dual nios with 2 tightly coupled code and 3 data blocks booted from the PCIe slave -> Avalon bridge. I had intended to dual port the 'shared data' directly between two tightly coupled data ports, but CPU B doesn't make that many accesses (when not idle) and isn't that time/clock critical so accessing via the Avalon bus lets me read it out over PCIe for debug/diagnostics.

The device also contains a big TDM switch, an FFT block for tone detect etc.

I'm also not sure which version or Quatus they hw guys use. I think they are frightened to change because something might break!