Dual access block ram access from nios and custom vhdl

Thank you! Using the template, I have been able to successfully read and write from vhdl to a block ram instantiated in sopc builder. I am still having a problem doing both at the same time though. What I mean by that is if I one design with read capability another design with write capability, both work fine. But when I attach two master templates (one for read, one for write) to one slave port of the block ram, the write (which works fine) interferes with the read. It seems like the read reads from the wrong address. Do I need some sort of arbitration? I thought this would be handled by the avalon logic?