Forum Discussion
Downloading ELF Process failed!
I am running NiosII IDE on my windows 7 professional laptop. When I first create a sopc project and complie and download *.sof into target board, then I also create a demo NiosII project "Hello world!" and debug it normally. Howerver, after I close NiosII IDE and restart it, I cann't debug it anymore eventhrough I don't change anything in both Quartus and sopc. It gives me a prompt that "Lanching hello_test Nios II hardware configuration has encourntered a problem. Downloading ELF Process failed". No matter I restart my laptop or power off my target board, it doesn't work! If I rebuild a new same sopc project and rebuild a new same NiosII project, it can work.But there is the same problem if I close it and restart it again. Please help me!:confused::confused::confused:
23 Replies
- Altera_Forum
Honored Contributor
Thuy,
You have two processors and two jtag_uarts then? You need to be sure that you've hooked up everything properly in SOPC Builder and then you need to tell the tools which processor you're downloading to and from which jtag_uart console will function. From the GUI, I'm not entirely sure how this would work, but from the command line their are arguments for both nios2-download and nios2-terminal that can deal with this... Good Luck! Slacker - Altera_Forum
Honored Contributor
Thank you so much for your reply, Slacker. I appreciate that.
Yes I did add cpu_0 and cpu_1 intentionally because I want to play 2 cores at the same time later. I did select with Eclipse from the time creating new project in C and when run as configuration, but the ELF loading still failed. Even when I deleted cpu_1 and juart_1, run as above and got same error. Notice that with the same sopc file I could see "hello world" with another version of board (unwanted version). So I believe the problem is in the hardware of the FPGA. but not sure what kind of things may happen? I checked very carefully the scheme. could not find yet. As I read, people talked much about clk and reset_n, but even with reset_n of onchip mem connected to Vcc it still worked with unwanted version board. another clue, the main difference vs. the worked board is : the init_done, config_done, nstatus n_config are pulled up to 3.3V with 10K (supposed to be right) all VCCD_PLL to 1.2V instead of 2.5 V (should be right too) many IO pins are set free instead of mislabled and connected to GND or VCCINT. It's so funny that the version with many mistakes worked and the corrected one does not work. Please suggest me something to investigate more. - Altera_Forum
Honored Contributor
Refresh Connections in Target Connection,if it still like before,close it and reconfiguration,it maybe OK.
- Altera_Forum
Honored Contributor
Hi,
I am currently working with the last version of the tools (Quartus II 10.1 SP1 and Nios II SBT 10.1 SP1) and I have to same problem as described initially in the thread: (...) Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x01201010: verified Initializing CPU cache (if present) OK Downloading 01100020 ( 0%) Downloading 01110000 (44%) Downloading 01120000 (89%) Downloaded 144KB in 2.4s (60.0KB/s) Verifying 01100020 ( 0%) Verify failed between address 0x1100020 and 0x110FFFF Leaving target processor paused (...) This always happens when the code size is above 64kB (0x00010000). Sometimes at the beginning, sometimes afterwards. But always during the veryfing process. The design I use is rather small (CPU + JTAG-UART + SYSID + AVALON-TRISTATE-BRIDGE + SRAM + CFI + PIO). I try the download command from the shell but th result is the same. When we "google" the error, we can see that it happens regularly since about the version 5. Did someone has a real clue or a workaround for this ? note that the code is working. i tested it by downloading it in the flash with the flash programmer. the problem only appears in debug (or run) mode. - Altera_Forum
Honored Contributor
"Downloading ELF Process failed"
I sometimes get this error usually when there is a mismatch between the ELF and the firmware I have loaded on the target board. (e.g. the BSP doesn't match the system that the ELF is expecting or the POF/SOF is old or wrong version) A quick check amost always shows that I have the wrong SOF/POF loaded on the target. Getting close (or exceeding) to memory size can cause problems too. - Altera_Forum
Honored Contributor
Hello,
there is solution for this. Please refer : https://www.altera.com/support/support-resources/knowledge-base/solutions/spr343469.html regards, Farabi - Altera_Forum
Honored Contributor
- Altera_Forum
Honored Contributor
Looks like your NIOS system does not have any memory configured at the addresses starting at 0x1000. You either need to put some memory there in QSYS/SOPC_Builder or use the NIOS linker script to load the data somewhere where you *do* have memory configured.
- Altera_Forum
Honored Contributor
Hello Babloo
several things you need to check for this-- Increase the memory size, check mark the small c library from BSP setting, and also check the interconnections specially between CPU and JTAG in your qsys model. Regards Rupok - Altera_Forum
Honored Contributor
Hi Rupok,
1. As there was a memory issue, self has chosen 'hello_world_small' template instead of 'hello_world' template. 2. And, the small c library is already enabled in BSP settings. 3. Regarding Qsys modelling, I've followed as per the instruction manual for beginners. But at the time of compilation, there is an issue here. Please refer the following thread for more details.. http://www.alteraforum.com/forum/showthread.php?t=51491 Kindly help in proceeding further. Thank you