Hello daixiwen,
Thanking you for reply,
1. Yes Design Properly Constrained and meet all timing requirements
2. Yes clocks present and at correct frequency.
3. reset signal is also correct.
I have add a three inputs (Start, Load and 8 bit data), coming out from different hardware module.
i am trying to use these there input in my C-code...for holding and further forward these data in UDP format to other terminal.
if i redesign the entire nios-2 Processor with the same configuration and port simple "hello world" there is no issue and nios-2 generate "hello World".
Regards
kaushal