Honored Contributor
Honored Contributorhttp://www.altera.com/literature/ug/ug_nio...instruction.pdf (http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf)
Go to page 17 (1-9). In that example you see 3 custom instruction blocks plus the N port. If you are not structuring your hardware this way then I would. So keep your custom logic the way it is, but bring their results through a MUX using n[1..0] to select them (so CC1 goes to the first MUX input, CC2 goes to the second MUX input, CC3 goes to the third MUX input, and ground the fourth MUX input). Why having the clock enable but not using it allows your design to work is beyond me, but if it is structure like in that pdf then you should have no problem. By the way, the external circuit that these custom instructions interface to, is it a combinational circuit too? (make sure that everything can be completed in a single clock cycle) Cheers
