Forum Discussion
Altera_Forum
Honored Contributor
21 years agoI was not clear in explaining the situation, sorry... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif
I have a Nios II project with 3 custom instructions. Each c.i. exports the signals to a single user logic, out of the Nios II core (but on the FPGA). Each c.i. performs a different operation on this logic. There is only one user logic, shared by the 3 custom instructions. In the user logic, I used 'clock' and 'reset' from the top level entity of the project, not from each c.i. Each c.i. is a fixed clock cycle operation and uses only 'start', 'dataa' and 'result'. I didn't use 'clock', 'clk_en' and 'reset'. For the moment, the project seems to work correctly. The question is: Is there the possibility that the Nios II core want to use the clk_en of each c.i. for some reasons? In this case it'll not work!!?!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif Bye