Do the DMA controller parameters in Qsys all function properly?

I am not very familiar with Nios-DMA designs. So do be patient with me.

How is the connection between the onchip-memory-DMA-SDRAM? Is there any sharing of onchip memory/SDRAM with Nios?

You can try to signal tap and see whether transactions at the onchip/SDRAM interface is ok, ie continuous transfer or back-pressure at the interface and root cause the back-pressure. Can you increase the size of the bytes sent? Just to get better average compared to smaller data bytes that can be highly affected by overhead.

How did you come up with the 2MB/sec? Do you have timer/performance counter?