DMA

this is my verilog soure

module crc_peripheral ( reset, clk, chipselect, write,read,

writedata, address, readdata);

input reset;

input clk;

input chipselect;

input write;

input read;

input [31:0] writedata;

input address;

output reg [31:0] readdata;

reg [15:0] crc_result;

reg [15:0] crc_reg;

//////////

// Set result output

//assign readdata = {16'h0, crc_reg};

/////////

// Initialise or update CRC reg based on address line

wire [15:0] crc_reg_input = (address) ? crc_result : writedata[15:0];

//////////

// CRC needs big endian data but Nios is little endian

// Convert data here

wire [15:0] crc_word = {writedata[7:0], writedata[15:8]};

wire [15:0] next_crc_word = {writedata[23:16], writedata[31:24]};

/////////

// CRC calculation

integer i;

reg [15:0] crc_array[0:16];

always @ (crc_word, next_crc_word)

begin

crc_array[16] = crc_reg;

for (i=15; i>=0; i=i-1)

begin

crc_array [0] = crc_array [i+1][15] ^ crc_word;

crc_array [1] = crc_array [i+1][0];

crc_array [2] = crc_array [i+1][1];

crc_array [3] = crc_array [i+1][2];

crc_array [4] = crc_array [i+1][3];

crc_array [5] = crc_array [i+1][4] ^ crc_array [0];

crc_array [6] = crc_array [i+1][5];

crc_array [7] = crc_array [i+1][6];

crc_array [8] = crc_array [i+1][7];

crc_array [9] = crc_array [i+1][8];

crc_array [10] = crc_array [i+1][9];

crc_array [11] = crc_array [i+1][10];

crc_array [12] = crc_array [i+1][11] ^ crc_array [0];

crc_array [13] = crc_array [i+1][12];

crc_array [14] = crc_array [i+1][13];

crc_array [15] = crc_array [i+1][14];

end

crc_array[16] = crc_array[0];

for (i=15; i>=0; i=i-1)

begin

crc_array [0] = crc_array [i+1][15] ^ next_crc_word;

crc_array [1] = crc_array [i+1][0];

crc_array [2] = crc_array [i+1][1];

crc_array [3] = crc_array [i+1][2];

crc_array [4] = crc_array [i+1][3];

crc_array [5] = crc_array [i+1][4] ^ crc_array [0];

crc_array [6] = crc_array [i+1][5];

crc_array [7] = crc_array [i+1][6];

crc_array [8] = crc_array [i+1][7];

crc_array [9] = crc_array [i+1][8];

crc_array [10] = crc_array [i+1][9];

crc_array [11] = crc_array [i+1][10];

crc_array [12] = crc_array [i+1][11] ^ crc_array [0];

crc_array [13] = crc_array [i+1][12];

crc_array [14] = crc_array [i+1][13];

crc_array [15] = crc_array [i+1][14];

end

crc_result <= crc_array [0];

end

// CRC Register

always @ (posedge clk or posedge reset)

begin

if (reset)

crc_reg <= 0;

else

if (write && chipselect)

crc_reg <= crc_reg_input;

end

always @ (posedge clk or posedge reset)

begin

if (reset)

readdata <= 0;

else

if (read && chipselect)

readdata <= {16&#39;h0,crc_reg};

end

endmodule