DMA

In "Post your own IP" there is the IP "streaming output register" to download. I think u could use it. I haven't try it yet.

bye

Nofi,

The streaming output register peripheral is sort of the opposite of what you want. It allows a DMA to write to it only once every <user-defined interval>. I think what you want is either

1) a pio which only allows a read once per 27MHz period (~37 ns)

2) a pio which only allows a read if the input data has changed.

If it&#39;s case 1), have you considered setting your system clock rate to 54MHz and having a simple 1 read-wait-state peripheral? That single wait state would force a DMA to throttle its read rate down to the required 27MHz.

If case 2) is what you want, you might be able to use an instance of the existing PIO component as a building block. I would proceed as follows:

a) create an instance of the Avalon PIO component, input only, set to interrupt on either edge

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif import the generated HDL for the PIO using the Component Editor - set most avalon ports with types as the are for a PIO, but change the type of the IRQ port to "dataavailable".

I&#39;m not sure of the details of how an IRQ is acknowledge in the Avalon PIO - you might need to make a small modification to the HDL so that the "IRQ" (actually, dataavailable) is cleared when you read from the data port.

Then you&#39;d program the DMA for a large transaction, and start it - it will read from the PIO whenever the PIO&#39;s dataavailable port goes active, and stall when there&#39;s no data.

By the way, I&#39;m assuming that your 27MHz data rate PIO is in the same clock domain as the DMA; if not, I think you will not be able to get the data transfer rate you&#39;re looking for, due to latency through the clock crossing adapter.

I had to make a few guess about what you&#39;re really after here - hopefully I&#39;m not completely off base. Let me know if any of these ideas make sense.

Kero,

I was reading your reply. Does crossing clock domains slow down the throughput that much? I am going to make a post on thsi, but, can I sustain streaming at 50 Mhz( SOPC domain) to LCD controller at 35 Mhz?

-Baycool

baycool,

I believe you&#39;ll see too much of a delay through the clock-crossing logic to sustain that data rate.

Kero,

The Nios sim I am running is okay with 50 Mhz to a 35 Mhz domain. Granted this is not P&R logic, but when I tried to run faster SOPC inserted wait states, I guess anticipating that this logic could not run faster.

In any case, what allowed my simualtion to run at speed was taking out the one clock write wait state.

I will see if this all works when I build real hardware.

-Baycool