DMA SDRAM burst read not working

I just posted this as a support service request...

We are using a SOPC Builder-instantiated DMA controller to interface between the SDRAM and a small on-chip cache of 1600 bytes. The DMA is controlled by a module we've created to write in 800 bytes at a time to the cache, while the module reads the other half simultaneously (dual port access).

This configuration currently works on the Cyclone development kit and it used to work on our custom board with an EP2C8 and Micron SDRAM. Something changed, but we don't know what.

After probing around with SignalTap, we found that the cache was being written to approximately once every 14-15 clock cycles. In the working configuration, this occurs much faster. At this rate, it misses its timing constraints - it only gets through half of the write before it must start reading new data. As of now, we have traced the cause of this back to the burst downstream port, created for the DMA read operation, which shows the downstream_waitrequest as high for the same amount of time.

We are wondering what might have caused this change in behavior, and how to fix it (or what to look for).

The DMA we instantiated is set as follows:

DMA length register is 9 bits

Burst transactions enabled

Maximum burst size is 512 words

Word transactions only enabled

FIFO constructed from embedded memory blocks

The cache is instantiated as follows:

RAM

Dual-port access

Width 32 bits

Total size 1600 bytes

Read latency 1 for s1 and s2

s1 connects to DMA write master

s2 connects to our module's read master

The SDRAM module we are using is the Micron MT48LC4M32B2 - 6

SDRAM controller is:

Width 32 bits

CS1 Banks 4

12 Rows 8 Columns

Not on a tristate bridge

CAS Latency 2

2 Init refresh cycles

15.625us between refresh

100us delay after powerup

t_rfc 60ns

t_rp 18ns

t_rcd 18ns

t_ac 7.5ns

t_wr 12ns

We are running the system at 50MHz, with a Nios II/f.