Forum Discussion
Altera_Forum
Honored Contributor
20 years agoHi Arjan,
> But the load on the Avalon bus is still too high, even with the Nios running in > on-chip RAM Keep in mind that internally, the DMA master and the cpu masters do not share a "common" bus per-se, but are rather muxed at the slave (under control of the avalon arbitration logic). That is, cpu access to the on chip ram does not interact with dma master access to the sdram. The only time they "interact" is when they are attempting to simultaneously access the same slave. Perhaps some of the avalon gurus could comment on this. If your cpu is running from on chip ram, it should not be accessing the sdram at all. Unless ... interrupts are enabled and being handled by exception code that is located in the sdram. Glad to hear you're making progress! Regards, --Scott