Altera_Forum
Honored Contributor
Honored ContributorDigital Pll
hi
any one can explain concept of digital pll and how to implement it in cyclone3Forum Discussion
4 Replies
Altera_ForumI would rather like to refer a profound text book phase-locked loops, design simulation and applications by Roland E. Best. Digital PLLs are just digital circuits, not specific to FPGA or Cyclone III in particular. Basically, digital PLLs are generating a time discrete signal within the system clock domain of the design. Analog PLLs, as available with most FPGAs create a new clock and a clock domain on their own.
P.S.: Some basic DPLL ideas can be found in this TI application notes: http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractname=sdla005b http://focus.ti.com/lit/an/slyt169/slyt169.pdf- Altera_Forum
hi..thank u for your reply..
my requirement is , i want to lock 32MHz clock from vcxo which is going to fpga with reference clock of 2MHz which is also coming to fpga.(ie both should be in sync) - Altera_Forum
hi..thank u for your reply..
my requirement is , i want to lock 32MHz clock from vcxo which is going to fpga with reference clock of 2MHz which is also coming to fpga.(ie both should be in sync) - Altera_Forum
To control the VXCO, a D/A converter would be required.
