Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
you could use a PIO-Core inside the QSYS-System, which is connectable with the NIOS and is generating an Interrupt which gets catched by the NIOS.
See in [1] for further details. Maybe there are also some reference designs for your board available with a PIO-Core connected?! Regards [1] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf - Altera_Forum
Honored Contributor
You are more than likely missing the pulsed signal. I was running into the same issue. I was providing the nios with a 1cc pulsed signal as an interrupt. The nios was on the same clock domain, but it was still missing it.
The solution was to use an active high level interrupt. This interrupt remains high until the nios acknowledges it, then the nios goes out and clears it. This was accomplished by writing to a "clear" register that I implemented in the interrupt generating component.