Design tree QIP->SDC is not present at the 'Files' tab of my new project

Regarding to the issue "missed qip->sdc tree at design" I found the root of the problem.

I was inserting an empty bloc having the same name than the current Nios2 design wrote in Qsys.

This also explains the error of "connected id hash and timestamp not found", of course, due there was no core there.

By the way, once I now made the things correctly, Quartus compiled the entire design, but unfortunatelly the amount of 30 MK4 resourses required to synthesize the design could not fit into my modest core ( EP2C5T144C8 ), which has only 26 MK4 , so it's clear that it is time to either upgrade my chip, or purchase a better development kit.

So, I can say that somehow the original problem, as stated, is solved.