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Altera_Forum's avatar
Altera_Forum
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16 years ago

Design for Multiple NIOS II

A question regarding consideration in HW design for best supporting (and best performance) of multiple NIOS II architecture. E.g:

* extrenal RAM accessed by multiple NIOS II CPUs : are performance degraded when accessed in parallel by several NIOS II CPUs? Is there a recommendation how tol solve it (multiple RAM chips/controllers) ?

* BUS limitations : what BUSes willsuffer from performance degradation due to the load of several CPUs ? How to solve ?

*External arbitters required ?

* ANy other comments / recommendations ?

Thanks,

Hed.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You should consider reading

    Computer Architecture, Fourth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) by Hennesy and Patterson