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Honored ContributorDesign consideration help - Memory tester
Hello,
I was hoping you could just review my design plan and tell me any relavent tips or lessons learned you might have. My board will have on chip memory, SDRAM and Flash. I'd like to fully test the SDRAM memory using a bit-walking pattern. To do this, the only way I can think of is to have two seperate programs, a memory tester and my actual system program. I'd boot initally into the memory tester, which would execute code out of Flash w/ heap & stack in on-chip memory. I'd store the results of this test in an external (to Nios) register, and then jump to {Flash + Main program offset}. My main program would run fully out of SDRAM (code/text, heap, stack, etc.) What do you think before I jump in head first (as this is my first Nios project, looks like a decently high jump). Thanks a bunch, Kevin6 Replies
Altera_ForumJust testing the memory with your CPU's data master (what you're doing with your proposed test) is not good enough. The data master cannot read from the memory as quickly as the CPU's instruction master. A DMA will help you to truly "exercise" your memory's limits.
Take a look at what the Memory Test software example is doing. It already provides something along the lines of what you're trying to do...you may want to modify it to suit your needs, rather than starting from scratch. Cheers, - slacker- Altera_Forum
Excellent point about the DMA. Yes, the memory interface should be tested fully as well.
the other half of the testing should be to fully test each individual bit in memory, which obviously isn't possible if I bootload into the SDRAM. So does the multi-program approach where the memory tester is loaded into on-chip memory make sense? Regards, Kevin - Altera_Forum--- Quote Start --- originally posted by kwolfe@Aug 8 2006, 08:39 AM excellent point about the dma. yes, the memory interface should be tested fully as well.
the other half of the testing should be to fully test each individual bit in memory, which obviously isn't possible if i bootload into the sdram. so does the multi-program approach where the memory tester is loaded into on-chip memory make sense?
regards,
kevin
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--- Quote End --- Certainly. You'd probably want to design a small piece code to run in on-chip RAM, that would fully exercise every bit in the memory. Cheers, - slacker
- Altera_Forum
I really appreciate your help slacker. Thanks.
Hopefully I can pick your (or anyone elses) brain for one last issue. I've loaded the mem test program onto my development board but adjusted it so that I'm running out of the ext_ram (SRAM) and am trying to exercise the test routine on the SDRAM. I'm running into an issue where I get data corruption (the program 'crashes') if I run the test on addresses starting at 0x0100.0000 (which is SDRAM_BASE). However, I have no issues running the test at 0x0100.01c8 (VMA + LMA as reported in the objdump) and beyond. Am I understanding it correctly that my SDRAM addresses are simply adjusted during the compile? Therefore, when I run the test at SDRAM_BASE, I'm in fact really adjusting some other memory in the system space? If so, is there any way to dynamically hard code in what the SDRAM addresses will be? Or am I just way off and have a seperate issue at hand. Thanks again, Keivn - Altera_Forum--- Quote Start --- originally posted by kwolfe@Aug 8 2006, 11:54 AM i really appreciate your help slacker. thanks.
hopefully i can pick your (or anyone elses) brain for one last issue. i've loaded the mem test program onto my development board but adjusted it so that i'm running out of the ext_ram (sram) and am trying to exercise the test routine on the sdram.
i'm running into an issue where i get data corruption (the program 'crashes') if i run the test on addresses starting at 0x0100.0000 (which is sdram_base). however, i have no issues running the test at 0x0100.01c8 (vma + lma as reported in the objdump) and beyond.
am i understanding it correctly that my sdram addresses are simply adjusted during the compile? therefore, when i run the test at sdram_base, i'm in fact really adjusting some other memory in the system space? if so, is there any way to dynamically hard code in what the sdram addresses will be? or am i just way off and have a seperate issue at hand.
thanks again,
keivn
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17450)
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--- Quote End --- You're probably overwriting the code located at your Exception Address. Change this to something other than SDRAM (in SOPC Builder) and recompile. Regarding your addressing question, it's absolute, but the switch fabric only makes the connections (master<=>slave) where necessary. SDRAM_BASE will always be SDRAM_BASE to those masters (CPU-IM, CPU-DM, DMA) that are connected to it. - slacker
- Altera_Forum--- Quote Start --- originally posted by slacker@Aug 8 2006, 04:08 PM you're probably overwriting the code located at your exception address. change this to something other than sdram (in sopc builder) and recompile. --- Quote End --- You nailed it. *smacks forhead* Thanks again, Kevin
