Delayed Interrupt

Actually, if you look at the timing trace you'll see that there is a relatively long time between the interrupt request and your ISR running.

Throw away the Altera interrupt code and write your own.

Even if you have to save/restore the registers it shouldn't take anywhere near the length of time that code takes.

If you can use an 'alternate register set' then you should be able to get interrupt entry/exit down to a few clocks.

(even without it you might manage to write an asm ISR that doesn't use any registers that the main code uses)

I also presume you are not running the JTAG debugger at all - it wouldn't surprise me if that doesn't take some interrupts.

You might also want to look at adding a short fifo (a couple of items) on the input and output - that will mean that the system will handle a longer interrupt latency.

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Open Qsys and go to Nios properties.

Add a tightly coupled (TC) code port and possibly a TC data port.

Close Nios properties.

Add 2 onchip memories and connect one of them to Nios TC code port and the other to TC data port.

In your case I believe 4kByte for TC code memory is enough.

TC data must be large enough to store ImgBuff, then size >= (460 x 640 x 4) if you need 32bit data; this would be more than 1MByte and probably exceeds your fpga resources, so you can not use TC data and you have to keep data in ddr2.

Now, let's say you named tc_code your TC memory component.

Then place the following directive just after the declaration of a function you want to be executed in TC memory:

int main(void) __attribute__ ((section (".tc_code")));

The same can be done with variable you want to be accessed very very fast:

int fastBuffer[256] __attribute__ ((section (".tc_data")));

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my Qsys not opening my sopc file it display only clock is it some kind of license issue i am using quartus 11.0 sp1

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my Qsys not opening my sopc file it display only clock is it some kind of license issue i am using quartus 11.0 sp1

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How did you design your system before?

IIRC Qsys in Quartus 11.0 doesn't open automatically the design and presents you the basic clock+reset default system; you simply have to load your actual design from File menu.

If the TC solution is not enough for you I'd follow dsl's tips, especially the alternate register set and the fifo.

You probably also want to arrange for the 'small data segment' to be in the on-chip memory and use section names ".sdata.*" so that the compiler will generate %gp relative addressing for the accesses.

Unfortunately the Altera builds of the compiler will not use %gp relative addressing for members of structures or arrays allocated to the 'small data' section. There are some gcc patches on the wiki that will make gcc use %gp relative addressing for structure members (constant offset from %gp), but not for arrays.

An alternative is to put all the global data inside a single structure (max 32kb) and use a global register variable to access it. gcc can generate better code for this than when using 'small data'. With care you can use %gp for the global register!