Altera_ForumHonored Contributor10 years agoDebugging of the FPGA portion using the HPS ARMs & Linux Hello All, I have three SPI cores instantiated in the FPGA portion and connected to the AXI3 Lightweight Bridge (ArriaV SX device). I need to start debugging them (write to SPI cor...Show More
Altera_ForumHonored Contributor10 years agohi,, adaptive debugging mode? https://www.youtube.com/watch?v=2nbcuv2txbi
Recent DiscussionsJTAG_UART stuck in printfNIOS SDK SBOM/FOSS infoNiosV µC/OS-IIRecommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"