Honored Contributor
Honored ContributorI'm going to bump this back up as I'm hitting the same problem and no answer has been given.
My design flow at the moment is to put the reset vector in ram and use this to debug my code. Once I'm happy, I recompile the hardware design, this time putting the reset vector in flash. I then program the flash with the new FPGA image and software image and test. Unfortunately, this then stops the debugger from working (ELF verify fail as below) so to debug I need to switch back to the reset vector being in ram. All a bit of a pain. This all appears to be non optimal and feels likely that I'm doing something wrong. Any ideas? ELF Verify fail: Verifying 00000020 ( 0%) Verifying 0000A580 (82%) Verifying 09720000 (99%) Verify failed between address 0x9720000 and 0x972001F Leaving target processor paused
