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Altera_Forum
Honored Contributor
Honored Contributorde2_system_v1.5 --> tut_DE2_SDRam
Is there a bug in the sourcecode, which listed in the "tut_DE2_SDRam_vhdl.pdf"-file under ..\DE2_System_v1.5\DE2_tutorials ??? I copy and paste the code in my new project and become the f...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- originally posted by katchins@Feb 7 2007, 03:38 AM http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif
after many days of looking at sdram clock skew details, many trial and error runs (changing clock delays), the answer is below (vhdl coding errror)....
my code now runs from sdram with altpll of -3ns.
how do we report this typo to altera/terasic? it's in both versions (1.4 and 1.5) of the documentation i've seen. --- Quote End --- Altera is aware of the error now and will correct the error in the new release http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif Thanks for pointing it out.
