de2_system_v1.5 --> tut_DE2_SDRam

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After many days of looking at SDRAM clock skew details, many trial and error runs (changing clock delays), the answer is below (VHDL coding errror)....

My code now runs from SDRAM with ALTPLL of -3ns.

How do we report this typo to Altera/Terasic? It&#39;s in both versions (1.4 and 1.5) of the documentation I&#39;ve seen.

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originally posted by arrive@Jan 25 2007, 12:18 PM

seems the assignment in vhdl is in the wrong direction. try

dram_ba_1 <= ba(1);
dram_ba_0 <= ba(0);
dram_udqm <= dqm(1);
dram_ldqm <= dqm(0);

instead of

ba <= (dram_ba_1 & dram_ba_0);
dqm <= (dram_udqm & dram_ldqm);

and it should work.

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