Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

de2_system_v1.5 --> tut_DE2_SDRam

Is there a bug in the sourcecode, which listed in the "tut_DE2_SDRam_vhdl.pdf"-file under ..\DE2_System_v1.5\DE2_tutorials ??? I copy and paste the code in my new project and become the f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Seems the assignment in VHDL is in the wrong direction. Try 

DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);

instead of 

BA <= (DRAM_BA_1 & DRAM_BA_0);
DQM <= (DRAM_UDQM & DRAM_LDQM);

And it should work.