Hi,
--- Quote Start ---
I'm guessing I may be able to go backwards if you are really saying the tool has gotten worse?
--- Quote End ---
Please refer to the attached files. Qsys flow requires about 40,000 Logic Cells. On the other hand, Sopc Builder requires only about 24,000 Logic Cells for the same design. And the Qsys_Mem_Access.jpg file shows that the Qsys interconnet requires 8 clocks to transfer the fetched code, and the Sopc_Mem_Access.jpg file shows that Avalon interconect requires only 2 clocks.
--- Quote Start ---
I have no requirement only a desire not to be on the bleeding edge and also not to be far out of date.
--- Quote End ---
Maybe, I will update my example to Linux 4.x, if I have enough time in my summer vacation :-).
Kazu