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Altera_Forum's avatar
Altera_Forum
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14 years ago

DE0-NIOS2 clock speed limit 50MHZ

Hi, have "problem". I have DE0 dev board. When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. When I try to add pll 50MHz - > works. But if I use more then 50MHz (pll ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

how did you apply the recommendations? Maybe we can have a look at your SOPC or Qsys design ?

What is the component concerned with the top failing path when you increase frequency so that the constraints are no more satisfied ?

You can try a minimal design where only Nios2 is present with JTAG SysID and external or even internal RAM, that will allow you to know what Fmax your Nios2 can reach on DE0.