DDR3 without leveling clock length

For each byte lane I routed it with DQS / DM a bit longer than DQ.

And pretty much matched the lengths of the ck p/n to the CA lines.

Seems to work, tests show plenty of margin.

I have 4 16bit wide chips hooked up to the HPS DDR3, using a T topology for CA.

The dual data are in a back to back arrangement with address mirroring.

And 1 16bit wide DDR3 chip connected to the FPGA fabric which is point to point.