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Altera_Forum's avatar
Altera_Forum
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11 years ago

DDR3 without leveling clock length

Hi everyone, I'm developing a board with a CycloneV and a DDR3 chip drive by the HPS memory controller. CycloneV does not support write leveling. I'm currently struggling to know exactly what r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

For each byte lane I routed it with DQS / DM a bit longer than DQ.

And pretty much matched the lengths of the ck p/n to the CA lines.

Seems to work, tests show plenty of margin.

I have 4 16bit wide chips hooked up to the HPS DDR3, using a T topology for CA.

The dual data are in a back to back arrangement with address mirroring.

And 1 16bit wide DDR3 chip connected to the FPGA fabric which is point to point.