Ddr2 Hpcii Controller Throughput

97% means that is the best case efficiency of the memory for my system. There are penalties like refresh cycles, initial read latency, etc... So 97% means that for every 100 clock cycles that read/write were asserted only three of those cycles had waitrequest asserted (local_ready = 0). I was using a local burst count of 2 but the HP2 controller has the option to make the local port non-bursting. If you provide a bunch of back to back sequential accesses the controller will bundle them into a single burst to provide to the PHY. Once you disable the bursting you can use arbitration share to make sure the arbiter doesn't let in other masters if a master is already performing a bunch of non-bursting accesses. You'll never truly hit 100% efficiency with SDRAM over a substantial period of time since there are always overhead command cycles that prevent data from being moved.