Ddr2 Hpcii Controller Throughput

Thank-you for the reply, BadOmen.

I guess the key comment in one of the attached is:

>>>>Because DDR SDRAM memories incur a penalty when switching banks or rows,

>>>>performance improves when they are accessed sequentially using bursts.

Your comments were:

>>>>I'm getting around 97% efficiency out of it. To max out the throughput you have to >>>>sequentially access it. If you randomly access it I think I was seeing an efficiency

>>>>between 33-40% (I forget off the top of my head).

So, would that mean that 97% is worst case read or write using

sequential accesses using bursts?

So, would that mean that you are at 97% and not 100% only

because of throughput degradation when eventually switching banks or rows(once at the end of a row say) and it is only at this point that we see the local_ready signal toggle?

Else where does this degrade from 100% and under what circumstances would we

see the local_ready signal toggle?

I will code something up shortly to test.

Thanks again.