DDR vs. SDR RAM...

Hi Ken,

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originally posted by kenland@Dec 22 2004, 01:47 PM

hi thomas,

in your analysis you have the nios+sdram controller consuming 11-3 = 8 clocks. that's 8 clocks of overhead. is this just to be expected as normal?

how much overhead would be added on say a coldfire or an arm or some other softcore? do all/most embedded processors add over 300% overhead to memory reads? i don't know for sure, but it doesn't sound right.

i'd like to establish this as either an oversight, a work in progress, or the way it is and then have it documented. the current literature promises either "single cycle" or ">1 clocks" to access sdram. (11 != 1)

thanks,

ken

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I do not think that a "real" processor would be that slow, but there would for sure be some clocks of delay too, when you have really RANDOM accesses. The Nios needs some cycles more, as it is very pipelined to achieve a high fmax (as Jesse / James pointed out).

This problem (that memory access that miss that cache add a large delay) is basically the reason why Intel added Hyperthreading to their Pentium 4: While the Pentium 4 is waiting for the data, he "simply" switches to another task, so it can do something useful during waiting. (Of course the Pentium 4 is a much more sophisticated architecture with out-of-order execution and such stuff, and a cache miss is there even a larger penalty, because the core operates at a much higher frequency (e.g. 3.6 GHz) then the memory (e.g. 400MHz), so you get easily delays in the range of about 50 to 100 CPU-clock-cycles).

Merry Christmas

Thomas

www.entner-electronics.com (http://www.entner-electronics.com)