Honored Contributor
Honored ContributorHi Ken,
when I look back at the diagram I already posted in the first thread regarding this topic, I see that the SDRAM-controller needs 3 clocks to assert CAS after he got chip-selected (internally). +2 clocks CAS-latency +1 clock from the SDRAM-controller (I suppose the input-registers from the SDRAM-data-bus) The remaining 5 cycles appears to get lost somewhere inside the Nios (the CAS to CAS-time was 11 cycles in the case I observed). Using DDR-SDRAM would not help at all, because it mainly increases the burst-rate (2bits per pin and clock instead of 1), but has basically the same latency-behavior. You wrote that you need a 15bit look-up-table. If there are really random values to look-up, there will be no suitable solution with nios+SDRAM, I think. I would recommend that you perform the look-up-task by dedicated "hardware" in the FPGA. There you may do some pipelining and achieve 1 value per clock with the SSRAM you mentioned some time ago. With a dedicated SDRAM-controller you could get also a better speed, but it is very difficult to get a high worst-case-performance with the SDRAM for really random accesses. (The orignal problem from dziegel were really predictable sequential accesses, were you can achieve almost 1 access per clock with a non-nios-solution.) Maybe we could help you more if we get more details from your application. Regards Thomas www.entner-electronics.com (http://www.entner-electronics.com)
