DDR vs. SDR RAM...

Hi Jesse,

I'm still confused as to why the timing diagrams in the SDRAM datasheet show that we can get data in a fraction of of the time it actually takes.

Once the chipselect and address are on the address bus its only a clock or three before the sdram chip has the data ready on the data bus. So where are the other 9-11 clocks consumed? Is there a 6+ clock delay for addresses eminating from the Nios onto the Avalon bus? Or are there long delays delivering the data back into the Nios?

It wasn't that long ago I was writing code on PC's running around 100 MHz with same PC100 memory and random memory reads were 50-60ns if I remember correctly. What gives?

Thanks,

Ken