DDR termination resistors

I am looking for a document that describes how to compute resistor values for DDR SDRAM termination, both serial and paralel.

At the moment I use the same termination values as on the nios development board cyclone ii edition (http://www.altera.com/products/devkits/altera/kit-nios-2c35.html).

Serial terminations (near the Cyclone chip) are:

10ohm for DQ15..0 and both DQS signals

24ohm for address and control signals

Parallel terminations (at the traces end) are:

56ohm for all signals

Are this values computed according to the trace impedance?

The Altera board probably uses a multilayer board with stripline traces, in which case the trace impedance can be round 56ohm. The Cyclone II documentation describes SSTL-2 pins to have 50ohm serial impedance. For details see cyclone ii documentation (http://www.altera.com/literature/lit-cyc2.jsp) at pages:

2-57 (83 of 448)

5-12 (114 of 448)

I computed the trace impedance for my 4-layer board (Microstrip traces) to be 82.8ohm. I used the zcalc (http://www.jnicolle.com/?page=lvds) software.

Termination on the development board seems to be SSTL-2 Class I. The Jedec standard specifies a 25ohm serial resistor and a 50ohm paralel resistor. For detail see cyclone ii documentation (http://www.altera.com/literature/lit-cyc2.jsp) at pages:

10-8 (274 of 448)

Final Questions:

1. What serial and parallel resistor values should I use?

2. How should I compute this values.

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