DDR SDRAM won't fit!

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When You generate DDR controller, the core also generates a TCL script. Run it.

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Hi Socrates,

I have an issue with fitting DDR SDRAM controller on Cyclone III (3C120). I am building a triple-speed Ethernet module using Qsys as per the altera example http://www.altera.com/support/examples/nios2/exm-tse-sgdma.html?gsa_pos=1&wt.oss_r=1&wt.oss=triple

speed ethernet 13.1

When I try to build my project in Quartus II, I see the following errors:

Error (165011): altmemphy pin placement was unsuccessful

Error (165024): The DQ group with DQS pin "mem_dqs_to_and_from_the_ddr2_bot[0]" has invalid DQ group assignments

..

Error (171000): Can't fit design in device

Prior to compiling my design, I had run the TCL script, generated by the Qsys. But still, the fitting error persists.

And, I do not see multiple instance of any design component in my top module. Also, I've a query regarding any modification that is required

to the TCL script, before I run it?

Thank you very much.