ddr_sdram problem

Not that I'm an expert when it comes to DDR but did you assign the DDR I/O to the correct banks? (not all I/O on the FPGA can drive DDR SSTL2 signals) If you are not aware of that you might want to take a look at a Nios II Cyclone II or Stratix II RoHS example design. Open the DDR and notice that only two banks of I/O are being use for the DDR signals.

Now if those errors are coming from an example design (std_2C35 suggests that it is) have you regenerated the system in SOPC Builder? The DDR IP uses paths to find the logic making up the controller so it could be that your logic isn't being pulled in correctly.

I hope one of those ideas helps. If not please indicate whether or not you are running a custom design or an example design provided in the kit.