Honored ContributorThe examples provided with the CycloneII Nios development kit use the PLL within SOPC builder to create the clocks for the DDR memory controller. I haven't had any success getting that to work when I try to adapt it.
I noticed that the DDR/DDR2 controller documentation, AN361, and AN398 show the use of an PLL in the top level VHDL construct, rather than inside the SOPC builder. Does anyone know why? - Jim
Honored ContributorNormally in a design you would have the PLL instantiated in the top level (the reference designs you are referring to before 5.1 had this configuration as well). The PLL is now available within SOPC Builder but by no means is this a requirement for your design to work. So to answer your question why the PLL component is available within SOPC Builder in the reference designs the answer is to keep the design contained within SOPC Builder (simplicity).
So whether it's in or outside of SOPC Builder doesn't really matter (i.e. you are running into some other issue). Check your DDR component to make sure it's setting up the scripts properly and that the timing is correct.
