DDR Critical Warning

Have you solved all the Critical warnings? We run into similar warnings.

Thank you very much!

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Hello everybody,

I am working with a cyclone III FPGA, when I add in my sopc system the ddr controller with the clock bridge all of the bottom messages appear. My system works up to 96 MHz and the ddr controller with 110MHz.

Anyone can give me some advice to fix them?

Many thanks.

ifdm

Critical Warning: PLL clock nios32|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock nios32|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions

Critical Warning: Timing requirements not met

Critical Warning: ALTMEMPHY PLL, nios32:nios32|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_rnk3:auto_generated|clk[1], when fed by another PLL, must have bandwidth mode set to High instead of Medium

Critical Warning: ALTMEMPHY PLL, nios32:nios32|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_rnk3:auto_generated|clk[2], when fed by another PLL, must have bandwidth mode set to High instead of Medium

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