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Altera_Forum's avatar
Altera_Forum
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14 years ago

DDR Critical Warning

Hello everybody, I am working with a cyclone III FPGA, when I add in my sopc system the ddr controller with the clock bridge all of the bottom messages appear. My system works up to 96 MHz and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The solution has been connecting the ddr controller clk to the general clock of the system instead of chaining two pll's, now both of them, the pll of the general system and the pll of the ddr controller are fed by the same clock.