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Altera_Forum
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13 years ago

DDR_afi_clk to PLL input ?

Hello, My scenario: I've a project with a DDR2 SDRAM controller, this controller gives me two clocks : .ddr2.afi_clk = 200 Mhz and .ddr2.afi_half_clk = 100 Mhz, I use th...