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Altera_Forum
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20 years ago

dataavailable / waitrequest questions

Hi all,

I'm interfacing a FTDI 245 to a Cyclone. I have an Avalon slave that kind of works but it's very picky and I have to set wait states and hold times just right to make it work.

I'm rewriting the component with flow control (dataavailable and readyfordata) right now but I'm running into a problem with dataavailable. My plan is to raise dataavailable when the chip says it has data and then lower dataavailable at the end of the read. Then, when the chip has toggled it's flag I raise dataavailable again. My question:

- When exactly should I lower dataavailable? If I do it too fast (e.g. one clock after the rising edge of read) the bus never reads anything. If I do it too late the bus keeps issuing read cycles too fast and I read the same data over and over. The manual says that dataavailable can only be deasserted at the "end of a cycle" but when is that?

Now I'm starting to wonder if the better thing to do would be to use dataavailable only to get the transfer started and then use waitrequest to hold off the bus until the chip is done with a transfer. That raises another question:

- How do I avoid indefinitely stalling the bus if a transfer gets cancelled on the sending side (PC)? Should I add a control signal to reset my component or is there something in the Avalon bus I can use (e.g. somehow send a reset to the slave device).

Thanks,

Andrew

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    --- Quote Start ---

    originally posted by queisser@Oct 13 2006, 05:00 AM

    hi all,

    i'm interfacing a ftdi 245 to a cyclone. i have an avalon slave that kind of works but it's very picky and i have to set wait states and hold times just right to make it work.

    i'm rewriting the component with flow control (dataavailable and readyfordata) right now but i'm running into a problem with dataavailable. my plan is to raise dataavailable when the chip says it has data and then lower dataavailable at the end of the read. then, when the chip has toggled it's flag i raise dataavailable again. my question:

    - when exactly should i lower dataavailable? if i do it too fast (e.g. one clock after the rising edge of read) the bus never reads anything. if i do it too late the bus keeps issuing read cycles too fast and i read the same data over and over. the manual says that dataavailable can only be deasserted at the "end of a cycle" but when is that?

    now i'm starting to wonder if the better thing to do would be to use dataavailable only to get the transfer started and then use waitrequest to hold off the bus until the chip is done with a transfer. that raises another question:

    - how do i avoid indefinitely stalling the bus if a transfer gets cancelled on the sending side (pc)? should i add a control signal to reset my component or is there something in the avalon bus i can use (e.g. somehow send a reset to the slave device).

    thanks,

    andrew

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18663)

    --- quote end ---

    --- Quote End ---

    Hi Andrew,

    I am beginner with NIOS.. I have to use the old code provided by our customer for the new project. There i am seeing &#39;wait_writerequest&#39; output port in port map of block-ram module. Actually nios core will update the ram and FPGA has to read the ram when required. I am a bit confused with &#39;wait_writerequest&#39; o/p port.. Usually block-ram wont provide this kind of ports.. Since you are talking on flow-control component.. i am wondering this particular block-ram access might be related flow controlled ram access.. Can you please give some details on flow control component.. and its manual.. I couldn&#39;t locate it SOPC component list.

    Thanks,

    Siva
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    --- Quote Start ---

    originally posted by siva prasad motamarri@Oct 12 2006, 09:54 PM

    hi andrew,

    i am beginner with nios.. i have to use the old code provided by our customer for the new project. there i am seeing &#39;wait_writerequest&#39; output port in port map of block-ram module. actually nios core will update the ram and fpga has to read the ram when required. i am a bit confused with &#39;wait_writerequest&#39; o/p port.. usually block-ram wont provide this kind of ports.. since you are talking on flow-control component.. i am wondering this particular block-ram access might be related flow controlled ram access.. can you please give some details on flow control component.. and its manual.. i couldn&#39;t locate it sopc component list.

    thanks,

    siva

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18664)

    --- quote end ---

    --- Quote End ---

    Siva,

    Flow control is not a component, just a feature of the Avalon bus. The manual that describes these things is the "Avalon Interface Specification", which you can find here: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf).

    I&#39;m sorry I can&#39;t be of any help with RAM components - haven&#39;t ventured into that territory yet - but with the bus spec and the other Altera literature that comes with the NIOS kit you will probably be able to figure out what is going on.

    Andrew